1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
A twin-well structure in which a P-well and an N-well are located adjacent to each other is used to form an N-type transistor and a P-type transistor on the same semiconductor substrate. It is desirable not to have a step at a boundary of the P-well and the N-well in order to improve the performance of a circuit element such as an LDMOS (Lateral Diffusion Metal Oxide Silicon) transistor and the like that are formed in the twin-well structure. The Japanese Patent Laid-Open No. 2006-190743 proposes a method of manufacturing a semiconductor device that does not have a step at the boundary of the N-well and the P-well. In this manufacturing method, after a phosphorous glass layer is formed on a semiconductor substrate, an opening is made in the phosphorous glass, and a P-type impurity layer is formed by an ion implanting a p-type impurity through the opening. Then, an N-type impurity layer is formed by having phosphorus contained in the phosphorous glass diffused into the semiconductor substrate by performing an annealing. The P-well and the N-well are then formed in the semiconductor substrate by performing drive-in diffusion of the P-type impurity layer and the N-type impurity layer.